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PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
PD703130
V850E/MS2TM 32-BIT SINGLE-CHIP MICROCONTROLLER
The PD703130 is a member of the V850 Family control operations.
TM
of 32-bit single-chip microcontrollers designed for real-time
These microcontrollers provide on-chip features, including a 32-bit CPU, RAM, interrupt
controller, real-time pulse unit, serial interface, A/D converter, and DMA controller. The PD703130 is a ROMless version product. Detailed function descriptions are provided in the following user's manuals. Be sure to read them before designing. V850E/MS2 User's Manual Hardware: V850E/MS1
TM
U14985E
User's Manual Architecture: U12197E
FEATURES
* Number of instructions: 81 * Minimum instruction execution time 30 ns (@ 33 MHz operation) * General-purpose registers 32 bits x 32 * Instruction set suitable for control applications * Internal memory ROM: None RAM: 4 KB * Advanced on-chip interrupt controller * Real-time pulse unit suitable for control operations * Powerful serial interface (on-chip dedicated baud rate generator) * On-chip clock generator * 10-bit resolution A/D converter: 4 channels * DMA controller: 4 channels * Power saving functions
APPLICATIONS
* Optical storage equipment (DVD players, etc.) * System control for digital consumer equipment, etc.
The information contained in this document is being issued in advance of the production cycle for the device. The parameters for the device may change before final production or NEC Corporation, at its own discretion, may withdraw the device prior to its production. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. U15390EJ1V0DS00 (1st edition) Date Published April 2001 N CP(K) Printed in Japan
(c)
2001
PD703130
ORDERING INFORMATION
Part Number Package 100-pin plastic LQFP (fine pitch) (14 x 14) Maximum Operating Frequency 33 MHz Internal ROM None
PD703130GC-8EU
PIN CONFIGURATION (TOP VIEW)
100-pin plastic LQFP (fine pitch) (14 x 14) * PD703130GC-8EU
D1 D0 VDD INTP103/DMARQ3/P07 INTP102/DMARQ2/P06 INTP101/DMARQ1/P05 INTP100/DMARQ0/P04 TCLR10/P02 TO100/P00 VSS INTP113/DMAAK3/P17 INTP112/DMAAK2/P16 INTP111/DMAAK1/P15 INTP110/DMAAK0/P14 TCLR11/P12 TO110/P10 TCLR12/P102 TO120/P100 ANI3/P73 ANI2/P72 ANI1/P71 ANI0/P70
AVDD AVSS AVREF
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
D2 D3 D4 D5 D6 D7 VSS D8/P50 D9/P51 D10/P52 D11/P53 D12/P54 D13/P55 D14/P56 D15/P57 HVDD A0 A1 A2 A3 A4 A5 A6 A7 VSS
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
A8 A9 A10 A11 A12 A13 A14 A15 A16/P60 A17/P61 A18/P62 A19/P63 A20/P64 A21/P65 A22/P66 A23/P67 HVDD CS0/P80 CS3/RAS3/P83 CS4/RAS4/IOWR/P84 CS5/RAS5/IORD/P85 LCAS/LWR/P90 UCAS/UWR/P91 RD/P92 WE/P93
2
NMI/P20 TXD0/SO0/P22 RXD0/SI0/P23 SCK0/P24 TXD1/SO1/P25 RXD1/SI1/P26 SCK1/P27 VDD INTP130/P34 TI13/P33 CVDD X2 X1 CVSS CKSEL MODE0 MODE2 RESET VSS CLKOUT/PX7 WAIT/PX6 HLDRQ/P97 HLDAK/P96 OE/P95 BCYST/P94
Preliminary Data Sheet U15390EJ1V0DS
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
PD703130
PIN NAMES
A0 to A23: ANI0 to ANI3: AVDD: AVREF: AVSS: BCYST: CKSEL: CLKOUT: CS0, CS3 to CS5: CVDD: CVSS: D0 to D15: DMAAK0 to DMAAK3: HLDAK: HLDRQ: HVDD: INTP110 to INTP113, INTP130 IORD: IOWR: LCAS: LWR: MODE0, MODE2: NMI: OE: I/O read strobe I/O write strobe Lower column address strobe Lower write strobe Mode Non-maskable interrupt request Output enable Address bus Analog input Analog power supply Analog reference voltage Analog ground Bus cycle start timing Clock generator operating mode select Clock output Chip select Clock generator power supply Clock generator ground Data bus DMA acknowledge Hold acknowledge Hold request Power supply for external pins P20, P22 to P27: P33, P34: P50 to P57: P60 to P67: P70 to P73: P80, P83 to P85: P90 to P97: P100, P102: PX6, PX7: RAS3 to RAS5: RD: RESET: RXD0, RXD1: SCK0, SCK1: SI0, SI1: SO0, SO1: TI13: TO100, TO110: TO120 TXD0, TXD1: UCAS: UWR: VDD: VSS: WAIT: WE: X1, X2: Transmit data Upper column address strobe Upper write strobe Power supply for internal unit Ground Wait Write enable Crystal Port 2 Port 3 Port 5 Port 6 Port 7 Port 8 Port 9 Port 10 Port X Row address strobe Read Reset Receive data Serial clock Serial input Serial output Timer input Timer output
DMARQ0 to DMARQ3: DMA request
TCLR10 to TCLR12: Timer clear
INTP100 to INTP103, : Interrupt request from peripherals
P00, P02, P04 to P07: Port 0 P10, P12, P14 to P17: Port 1
Preliminary Data Sheet U15390EJ1V0DS
3
PD703130
INTERNAL BLOCK DIAGRAM
CPU NMI INTP100 to INTP103 INTP110 to INTP113 INTP130 INTC
BCU HLDRQ HLDAK CS0,CS3 to CS5 RAS3 to RAS5 IOWR IORD BCYST WE RD OE UWR/UCAS LWR/LCAS WAIT A0 to A23 D0 to D15 DMARQ0 to DMARQ3 DMAAK0 to DMAAK3
Instruction queue PC
System registers
Multiplier (32 x 3264) Barrel shifter
DRAMC
TO100,TO110, TO120
RPU
RAM
General-purpose registers (32 bits x 32) ALU
PageROM controller
TCLR10 to TCLR12 TI13 SIO SO0/TXD0 SI0/RXD0 SCK0 UART0/CSI0 BRG0 SO1/TXD1 SI1/RXD1 SCK1
4 KB
DMAC
UART1/CSI1 BRG1
Port CG
ANI0 to ANI3 AVREF AVSS AVDD
ADC
PX6,PX7 P100,P102 P90 to P97 P80,P83 to P85 P70 to P73 P60 to P67 P50 to P57 P33,P34 P22 to P27 P20 P10,P12,P14 to P17 P00,P02,P04 to P07 HVDD
CKSEL CLKOUT X1 X2 CVDD CVSS MODE0,MODE2 RESET VDD VSS
System controller
4
Preliminary Data Sheet U15390EJ1V0DS
PD703130
CONTENTS
1. 2.
DIFFERENCES BETWEEN V850E/MS2 AND V850E/MS1............................................................ PIN 2.1 2.2 2.3 FUNCTIONS ............................................................................................................................. Port Pins ................................................................................................................................. Non-Port Pins ......................................................................................................................... Pin I/O Circuits and Recommended Connection of Unused Pins.....................................
6 7 7 9 11 14 68 69
3. 4. 5.
ELECTRICAL SPECIFICATIONS ................................................................................................... PACKAGE DRAWING ..................................................................................................................... RECOMMENDED SOLDERING CONDITIONS .............................................................................
Preliminary Data Sheet U15390EJ1V0DS
5
PD703130
1. DIFFERENCES BETWEEN V850E/MS2 AND V850E/MS1
Product Name Item Internal ROM Maximum operating frequency Memory space Chip select output Interrupt function I/O lines Timer Serial interface None 33 MHz V850E/MS2 V850E/MS1
PD703130
PD703100-33
None 33 MHz
PD703102-33
128 KB (mask ROM)
64 MB linear (only 22 MB supports on-chip CS signal) 4 spaces External: 10, internal: 35 Input: 5, I/O: 52 16-bit timer/event counter: 4 channels 16-bit timer: 2 channels CSI/UART: 2 channels Dedicated baud rate generator: 2 channels 10-bit resolution x 4 channels 100-pin plastic LQFP (fine-pitch) (14 x 14)
64 MB linear 8 spaces External: 25, internal: 47 Input: 9, I/O: 114 16-bit timer/event counter: 6 channels 16-bit timer: 2 channels CSI: 2 channels CSI/UART: 2 channels Dedicated baud rate generator: 3 channels 10-bit resolution x 8 channels 144-pin plastic LQFP (fine-pitch) (20 x 20)
A/D converter Package Other
Noise tolerance and noise radiation will differ due to differences in circuit scale and mask layout.
6
Preliminary Data Sheet U15390EJ1V0DS
PD703130
2. PIN FUNCTIONS 2.1 Port Pins
(1/2)
Pin Name P00 P02 P04 P05 P06 P07 P10 P12 P14 P15 P16 P17 P20 P22 P23 P24 P25 P26 P27 P33 P34 P50 to P57 I/O I/O Port 3 2-bit I/O port Input/output can be specified in 1-bit units. Port 5 8-bit I/O port Input/output can be specified in 1-bit units. Port 6 8-bit I/O port Input/output can be specified in 1-bit units. Port 7 4-bit input only port Port 8 4-bit I/O port Input/output can be specified in 1-bit units. Input I/O Port 2 P20 is an input only port. When a valid edge is input, this pin operates as NMI input. Also, bit 0 of the P2 register indicates the NMI input status. P22 to P27 are 6-bit I/O port. Input/output can be specified in 1-bit units. I/O Port 1 6-bit I/O port Input/output can be specified in 1-bit units. I/O I/O Function Port 0 6-bit I/O port Input/output can be specified in 1-bit units. Alternate Function TO100 TCLR10 INTP100/DMARQ0 INTP101/DMARQ1 INTP102/DMARQ2 INTP103/DMARQ3 TO110 TCLR11 INTP110/DMAAK0 INTP111/DMAAK1 INTP112/DMAAK2 INTP113/DMAAK3 NMI TXD0/SO0 RXD0/SI0 SCK0 TXD1/SO1 RXD1/SI1 SCK1 TI13 INTP130 D8 to D15
P60 to P67
I/O
A16 to A23
P70 to P73 P80 P83 P84 P85
Input I/O
ANI0 to ANI3 CS0 CS3/RAS3 CS4/RAS4/IOWR CS5/RAS5/IORD
Preliminary Data Sheet U15390EJ1V0DS
7
PD703130
(2/2)
Pin Name P90 P91 P92 P93 P94 P95 P96 P97 P100 P102 PX6 PX7 I/O I/O Port 10 2-bit I/O port Input/output can be specified in 1-bit units. Port X 2-bit I/O port Input/output can be specified in 1-bit units. I/O I/O Function Port 9 8-bit I/O port Input/output can be specified in 1-bit units. Alternate Function LCAS/LWR UCAS/UWR RD WE BCYST OE HLDAK HLDRQ TO120 TCLR12 WAIT CLKOUT
8
Preliminary Data Sheet U15390EJ1V0DS
PD703130
2.2 Non-Port Pins
(1/2)
Pin Name TO100 TO110 TO120 TCLR10 TCLR11 TCLR12 TI13 INTP100 INTP101 INTP102 INTP103 INTP110 INTP111 INTP112 INTP113 INTP130 SO0 SO1 SI0 SI1 SCK0 SCK1 TXD0 TXD1 RXD0 RXD1 D0 to D7 D8 to D15 A0 to A15 A16 to A23 LWR UWR RD WE OE Output Output Output Output Output Lower byte write-enable signal output for external data bus Higher byte write-enable signal output for external data bus Read strobe signal output for external data bus Write enable signal output for DRAM Output enable signal output for DRAM Output 24-bit address bus for external memory I/O 16-bit data bus for external memory Input Serial receive data input for UART0 and UART1 Output Serial transmit data output for UART0 and UART1 I/O Serial clock I/O (3-wire) for CSI0 and CSI1 Input Serial receive data input (3-wire) for CSI0 and CSI1 Input Output External maskable interrupt request input, shared as external capture trigger input for timer 13 Serial transmit data output (3-wire) for CSI0 and CSI1 Input External maskable interrupt request input, shared as external capture trigger input for timer 11 Input Input External count clock input for timer 13 External maskable interrupt request input, shared as external capture trigger input for timer 10 Input External clear signal input for timers 10 to 12 I/O Output Function Pulse signal output for timers 10 to 12 Alternate Function P00 P10 P100 P02 P12 P102 P33 P04/DMARQ0 P05/DMARQ1 P06/DMARQ2 P07/DMARQ3 P14/DMAAK0 P15/DMAAK1 P16/DMAAK2 P17/DMAAK3 P34 P22/TXD0 P25/TXD1 P23/RXD0 P26/RXD1 P24 P27 P22/SO0 P25/SO1 P23/SI0 P26/SI1 - P50 to P57 - P60 to P67 P90/LCAS P91/UCAS P92 P93 P95
Preliminary Data Sheet U15390EJ1V0DS
9
PD703130
(2/2)
Pin Name LCAS UCAS RAS3 RAS4 RAS5 BCYST CS0 CS3 CS4 CS5 WAIT IOWR IORD DMARQ0 to DMARQ3 DMAAK0 to DMAAK3 HLDAK HLDRQ ANI0 to ANI3 NMI CLKOUT CKSEL MODE0, MODE2 RESET X1 X2 AVREF AVDD AVSS CVDD CVSS VDD HVDD VSS Input Output Output Input Output Output Input Input Input Output Input Input Input Input - Input - - - - - - - Control signal input for inserting waits in bus cycle DMA write strobe signal output DMA read strobe signal output DMA request signal input DMA acknowledge signal output Bus hold acknowledge output Bus hold request input Analog input to A/D converter Non-maskable interrupt request input System clock output Input for specifying clock generator's operation mode Specify operation modes System reset input Connecting resonator for system clock. Input is via X1 when using an external clock. Reference voltage input for A/D converter Positive power supply for A/D converter Ground potential for A/D converter Positive power supply for dedicated clock generator Ground potential for dedicated clock generator Positive power supply (power supply for internal units) Positive power supply (power supply for external pins) Ground potential Output Output Strobe signal output indicating start of bus cycle Chip select signal output I/O Output Output Output Function Column address strobe signal output for DRAM's lower data Column address strobe signal output for DRAM's higher data Row address strobe signal output for DRAM Alternate Function P90/LWR P91/UWR P83/CS3 P84/CS4/IOWR P85/CS5/IORD P94 P80 P83/RAS3 P84/RAS4/IOWR P85/RAS5/IORD PX6 P84/RAS4/CS4 P85/RAS5/CS5 P04/INTP100 to P07/INTP103 P14/INTP110 to P17/INTP113 P96 P97 P70 to P73 P20 PX7 - - - - - - - - - - - - -
10
Preliminary Data Sheet U15390EJ1V0DS
PD703130
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins
Table 2-1 shows the I/O circuit type of each pin and recommended connection of unused pins. Figure 2-1 shows the various circuit types using partially abridged diagrams. When connecting to VDD or VSS via a resistor, a resistance value in the range of 1 to 10 k is recommended. Table 2-1. I/O Circuit Type of Each Pin and Recommended Connection of Unused Pins (1/2)
Pin P00/TO100 P02/TCLR10 P04/INTP100/DMARQ0 to P07/INTP103/DMARQ3 P10/TO110 P12/TCLR11 P14/INTP110/DMAAK0 to P17/INTP113/DMAAK3 P20/NMI P22/TXD0/SO0 P23/RXD0/SI0 P24/SCK0 P25/TXD1/SO1 P26/RXD1/SI1 P27/SCK1 P33/TI13 P34/INTP130 P50/D8 to P57/D15 P60/A16 to P67/A23 P70/ANI0 to P73/ANI3 P80/CS0, to P83/CS3/RAS3 P84/CS4/RAS4/IOWR, P85/CS5/RAS5/IORD P90/LCAS/LWR P91/UCAS/UWR P92/RD P93/WE P94/BCYST P95/OE P96/HLDAK P97/HLDRQ P100/TO120 P102/TCLR12 9 5 Connect directly to VSS Input: Independently connect to HVDD or VSS via a resistor Output: Leave open 2 5 Connect directly to VSS Input: Independently connect to HVDD or VSS via a resistor Output: Leave open I/O Circuit Type 5 Recommended Connection of Unused Pins Input: Independently connect to HVDD or VSS via a resistor Output: Leave open
Preliminary Data Sheet U15390EJ1V0DS
11
PD703130
Table 2-1. I/O Circuit Type of Each Pin and Recommended Connection of Unused Pins (2/2)
Pin PX6/WAIT PX7/CLKOUT A0 to A15 D0 to D7 CKSEL RESET MODE0, MODE2 AVREF, AVSS AVDD - - Connect directly to VSS Connect directly to HVDD 4 5 1 2 I/O Circuit Type 5 Recommended Connection of Unused Pins Input: Independently connect to HVDD or VSS via a resistor Output: Leave open -
12
Preliminary Data Sheet U15390EJ1V0DS
PD703130
Figure 2-1. Pin I/O Circuits
Type 1 Type 5 VDD VDD Data P-ch IN N-ch Output disable N-ch P-ch IN/OUT
Input enable
Type 2
Type 9
P-ch IN IN N-ch + - Comparator
VREF (threshold voltage)
Input enable Schmitt-triggered input with hysteresis characteristics Type 4 VDD Data P-ch OUT Output disable N-ch
Push-pull output with possible high-impedance output (P-ch, N-ch both off)
Caution Replace VDD by HVDD when referencing the circuit diagrams shown above.
Preliminary Data Sheet U15390EJ1V0DS
13
PD703130
3. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25C)
Parameter Power supply voltage Symbol VDD HVDD CVDD CVSS AVDD AVSS Input voltage Clock input voltage Output current, low VI VK IOL VDD pin HVDD pin, HVDD VDD CVDD pin CVSS pin AVDD pin AVSS pin Except X1 pin X1, VDD = 3.0 to 3.6 V 1 pin Total of all pins Output current, high IOH 1 pin Total of all pins Output voltage Analog input voltage VO VIAN HVDD = 5.0 V 10% P70/ANI0 to P73 pins AVDD > HVDD HVDD AVDD TA Tstg AVDD > HVDD HVDD AVDD Condition Rating -0.5 to +4.6 -0.5 to +7.0 -0.5 to +4.6 -0.5 to +0.5 -0.5 to HVDD + 0.5 -0.5 to +0.5 -0.5 to HVDD + 0.5 -0.5 to VDD + 1.0 4.0 100 -4.0 -100 -0.5 to HVDD + 0.5 -0.5 to HVDD + 0.5 -0.5 to AVDD + 0.5
Note Note Note Note
Unit V V V V V V V V mA mA mA mA V V V V V C C
Note
Note Note
A/D converter reference input voltage Operating ambient temperature Storage temperature
AVREF
-0.5 to HVDD + 0.5 -0.5 to AVDD + 0.5 -40 to +85 -60 to +150
Note
Note Be sure not to exceed the absolute maximum ratings (MAX. value) of the each power supply voltage. Cautions 1. Do not make direct connections of the output (or input/output) pins of the IC product with each other, and also avoid direct connections to VDD, VCC, or GND. However, the open drain pins or the open collector pins can be directly connected to each other. A direct connection can also be made for an external circuit designed with timing specifications that prevent conflicting output from pins subject to a high-impedance state. 2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. The ratings and conditions shown below for DC characteristics and AC characteristics are within the range for normal operation and quality assurance.
14
Preliminary Data Sheet U15390EJ1V0DS
PD703130
Capacitance (TA = 25C, VDD = HVDD = CVDD = VSS = 0 V)
Parameter Input capacitance I/O capacitance Output capacitance Symbol CI CIO CO Condition fc = 1 MHz Unmeasured pins returned to 0 V. MIN. TYP. MAX. 15 15 15 Unit pF pF pF
Operating Conditions
Operation Mode Internal Operating Clock Frequency (fX)
Note 1 Note 3
Operating Ambient Temperature (TA) -40 to +85C -40 to +85C
Power Supply Voltage (VDD, HVDD) VDD = 3.0 to 3.6 V, HVDD = 5.0 V 10%
Direct mode PLL mode
Note 2
10 to 33 MHz
20 to 33 MHz
Notes 1. Set the input clock frequency used in direct mode to 20 to 66 MHz. 2. The internal operating clock frequency in PLL mode is the value for 5x operation. When used for 1x or 1/2x operation as set by the CKDIVn (n = 0, 1) bit of the CKC register, operation at a frequency of 20 MHz or less is possible. 3. Set the input clock frequency used in PLL mode to 4.0 to 6.6 MHz.
Preliminary Data Sheet U15390EJ1V0DS
15
PD703130
Recommended Oscillator
(a) Ceramic resonator (i) Murata Mfg. Co., Ltd. (TA = -40 to +85C)
X1
X2 Rd C1 C2
Manufacturer
Part Number
Oscillation Frequency fXX (MHz) 4.0 4.0 5.0 5.0 6.6 6.6
Recommended Circuit Constant C1 (pF) On-chip On-chip On-chip On-chip On-chip On-chip C2 (pF) On-chip On-chip On-chip On-chip On-chip On-chip Rd (k) 0 0 0 0 0 0
Oscillation Voltage Range MIN. (V) 3.0 3.0 3.0 3.0 3.0 3.0 MAX. (V) 3.6 3.6 3.6 3.6 3.6 3.6
Oscillation Stabilization Time (MAX.) TOST (ms) 0.6 0.6 0.6 0.6 0.6 0.6
Murata Mfg.
CSTS400MG06
Note
(CSTLS4M00G56-B0) CSTCR4M00G55-R0 CSTS0500MG06
Note
(CSTLS5M00G56-B0) CSTCR5M00G55-R0 CSTS066MG06
Note
(CSTLS6M60G56-B0) CSTCR6M60G55-R0
Note The part number will be changed to the part number in the parentheses from June 2001. Cautions 1. Connect the oscillator as close to the X1 and X2 pins as possible. 2. Do not wire any other signal lines in the area enclosed by broken lines. 3. Sufficiently evaluate the matching between the PD703130 and the resonator.
16
Preliminary Data Sheet U15390EJ1V0DS
PD703130
(ii) TDK (TA = -40 to +85C)
X1
X2 Rd C1 C2
Manufacturer
Part Number
Oscillation Frequency fXX (MHz) 4.0 5.0 6.0
Recommended Circuit Constant C1 (pF) On-chip On-chip On-chip C2 (pF) On-chip On-chip On-chip Rd (k) 0 0 0
Oscillation Voltage Range MIN. (V) MAX. (V) 3.0 3.0 3.0 3.6 3.6 3.6
Oscillation Stabilization Time (MAX.) TOST (ms) 0.73 0.68 0.58
TDK
FCR4.0MC5 FCR5.0MC5 FCR6.0MC5
Cautions
1. Connect the oscillator as closely to the X1 and X2 pins as possible. 2. Do not wire any other signal lines in the area enclosed by broken lines. 3. Sufficiently evaluate the matching between the PD703130 and the resonator.
(iii) Kyocera Corporation (TA = -20 to +80C)
X1
X2 Rd C1 C2
Type
Part Number
Oscillation Frequency fXX (MHz) 4.0 5.0 6.0 4.0 5.0 6.0
Recommended Circuit Constant C1 (pF) On-chip On-chip On-chip On-chip On-chip On-chip C2 (pF) On-chip On-chip On-chip On-chip On-chip On-chip Rd (k) 0 0 0 0 0 0
Oscillation Voltage Range MIN. (V) 3.0 3.0 3.0 3.0 3.0 3.0 MAX. (V) 3.6 3.6 3.6 3.6 3.6 3.6
Oscillation Stabilization Time (MAX.) TOST (ms) 0.80 0.70 0.76 0.80 0.70 0.76
Lead
KBR-4.0MKC KBR-5.0MKC KBR-6.0MKC
SMD
PBRC4.00HR PBRC5.00HR PBRC6.00HR
Cautions
1. Connect the oscillator as close to the X1 and X2 pins as possible. 2. Do not wire any other signal lines in the area enclosed by broken lines. 3. Sufficiently evaluate the matching between the PD703130 and the resonator.
Preliminary Data Sheet U15390EJ1V0DS
17
PD703130
(b) External clock input (TA = -40 to +85C)
X1
X2 Open
External clock
Caution Input CMOS-level voltage to the X1 pin.
18
Preliminary Data Sheet U15390EJ1V0DS
PD703130
DC Characteristics (TA = -40 to +85C, VDD = CVDD = 3.0 to 3.6 V, HVDD = 5.0 10%, VSS = 0 V)
Parameter Input voltage, high Symbol VIH Condition Except Note 1 Note 1 Input voltage, low VIL Except Note 1 and Note 2 Note 1 Clock input voltage, high Clock input voltage, low Schmitt-triggered input threshold voltage Output voltage, high VXH VXL HVT
+
MIN. 2.2 0.8HVDD -0.5 -0.5 0.8VDD -0.3
TYP.
MAX. HVDD + 0.3 HVDD + 0.3 +0.8 0.2HVDD VDD + 0.3 0.15VDD
Unit V V V V V V V V V V
X1 pin X1 pin Note 1, rising edge Note 1, falling edge IOH = -2.5 mA IOH = -100 A
3.0 2.0 0.7HVDD HVDD - 0.4 0.45 10 -10 10 -10
HVT- VOH
Output voltage, low Input leakage current, high Input leakage current, low Output leakage current, high Output leakage current, low Power supply current Normal mode HALT mode
VOL ILIH ILIL ILOH ILOL IDD1
IOL = 2.5 mA VI = HVDD, except Note 2 VI = 0 V, except Note 2 VO = HVDD VO = 0 V VDD + CVDD HVDD 2.0 x fx 1.5 x fx 1.4 x fx 0.7 x fx 1.4 20 20 10
V
A A A A
mA mA mA mA mA
3.0 x fx 2.5 x fx 1.8 x fx 1.2 x fx 2.5 100 100 50
IDD2
VDD + CVDD HVDD
IDLE mode
IDD3
VDD + CVDD HVDD
A A A
STOP mode
IDD4
VDD + CVDD HVDD
Notes 1. P20/NMI, MODE0, MODE2, CKSEL, RESET 2. When the P70/ANI0 to P73/ANI3 pins are used as analog input. Remarks 1. TYP. values are reference values for when TA = 25C, VDD = CVDD = 3.3 V, and HVDD = 5.0 V. 2. Direct mode: fX = 10 to 33 MHz PLL mode: fX = 20 to 33 MHz 3. The unit for fX is MHz.
Preliminary Data Sheet U15390EJ1V0DS
19
PD703130
Data Hold Characteristics (TA = -40 to +85C)
Parameter Data hold voltage Symbol VDDDR HVDDDR Data hold current Power supply voltage rise time Power supply voltage fall time Power supply voltage hold time (from STOP mode setting) STOP mode release signal input time Data hold input voltage, high Data hold input voltage, low IDDDR tRVD tFVD tHVD Condition STOP mode, VDD = VDDDR STOP mode, HVDD = HVDDDR VDD = VDDDR 200 200 0 MIN. 1.5 VDDDR 30 TYP. MAX. 3.6 5.5 150 Unit V V
A s s
ms
tDREL VIHDR VILDR P20/NMI, MODE0, MODE2, CKSEL, RESET P20/NMI, MODE0, MODE2, CKSEL, RESET
0 0.8HVDDDR 0 HVDDDR 0.2HVDDDR
ns V V
Remark TYP. values are reference values for when TA = 25C.
STOP mode setting
3.0 V VDD tFVD tHVD VDDDR tRVD tDREL
HVDD
RESET (Input)
VIHDR
NMI (Input) (Released by falling edge)
VIHDR
NMI (Input) (Released by rising edge) VILDR
20
Preliminary Data Sheet U15390EJ1V0DS
PD703130
AC Characteristics (TA = -40 to +85C, VDD = CVDD = 3.0 to 3.6 V, HVDD = 5.0 10%, VSS = 0 V, output pin load capacitance: CL = 50 pF) AC Test Input Test Points (a) P20/NMI, MODE0, MODE2, CKSEL, RESET
HVDD Input signal 0V 0.2HVDD
0.8HVDD
Test points
0.8HVDD 0.2HVDD
(b) Pins other than those listed in (a) above
2.4 V Input signal 0.4 V 0.8 V 2.2 V 2.2 V 0.8 V
Test points
AC Test Output Test Points
2.4 V Output signal 0.8 V 2.4 V 0.8 V
Test points
Load Condition
DUT (Device under test) CL = 50 pF
Caution In cases where the load capacitance is greater than 50 pF due to the circuit configuration, insert a buffer or other element to reduce the device's load capacitance 50 pF.
Preliminary Data Sheet U15390EJ1V0DS
21
PD703130
(1) Clock timing
Parameter X1 input cycle Symbol <1> tCYX Condition Direct mode PLL mode X1 input high-level width <2> tWXH Direct mode PLL mode X1 input low-level width <3> tWXL Direct mode PLL mode X1 input rise time <4> tXR Direct mode PLL mode X1 input fall time <5> tXF Direct mode PLL mode CLKOUT output cycle CLKOUT high-level width CLKOUT low-level width CLKOUT rise time CLKOUT fall time <6> <7> <8> <9> <10> tCYK tWKH tWKL tKR tKF 30 0.5T - 7 0.5T - 4 5 5 MIN. 15 150 5 50 5 50 4 10 4 10 100 MAX. 50 250 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Remark T = tCYK
<1> <2> <4> X1 (PLL mode) <1> <2> <4> X1 (Direct mode) <5> <3> <5> <3>
CLKOUT (Output) <9> <7> <6> <10> <8>
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Preliminary Data Sheet U15390EJ1V0DS
PD703130
(2) Output waveform (other than X1, CLKOUT)
Parameter Output rise time Output fall time Symbol <12> <13> tOR tOF Condition MIN. MAX. 10 10 Unit ns ns
<12>
<13>
Signals other than X1, CLKOUT
(3) Reset timing
Parameter RESET high-level width RESET low-level width Symbol <14> <15> tWRSH tWRSL When power supply is on, and STOP mode has been released Other than when power supply is on, and STOP mode has been released Condition MIN. 500 500 + TOS 500 MAX. Unit ns ns ns
Remark TOS: Oscillation stabilization time
<14>
<15>
RESET (Input)
Preliminary Data Sheet U15390EJ1V0DS
23
PD703130
(4) SRAM, external ROM, or external I/O access timing (a) Access timing (SRAM, external ROM, or external I/O) (1/2)
Parameter Address, CSn output delay time (from CLKOUT ) Address, CSn output hold time (from CLKOUT ) RD, IORD delay time (from CLKOUT ) RD, IORD delay time (from CLKOUT ) UWR, LWR, IOWR delay time (from CLKOUT ) UWR, LWR, IOWR delay time (from CLKOUT ) BCYST delay time (from CLKOUT ) BCYST delay time (from CLKOUT ) WAIT setup time (to CLKOUT ) WAIT hold time (from CLKOUT ) Data input setup time (to CLKOUT ) Data input hold time (from CLKOUT ) Data output delay time (from CLKOUT ) Data output hold time (from CLKOUT ) Symbol <16> <17> <18> <19> <20> <21> <22> <23> <24> <25> <26> <27> <28> <29> tDKA tHKA tDKRDL tHKRDH tDKWRL tHKWRH tDKBSL tHKBSH tSWK tHKW tSKID tHKID tDKOD tHKOD Condition
MIN. MAX.
Unit ns ns ns ns ns ns ns ns ns ns ns ns
2 2 2 2 2 2 2 2 15 2 18 2 2 2
10 10 14 14 10 10 10 10
10 10
ns ns
Remarks 1. Maintain at least one of the data input hold times tHKID and tHRDID. 2. n = 0, 3 to 5
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Preliminary Data Sheet U15390EJ1V0DS
PD703130
(a) Access timing (SRAM, external ROM, or external I/O) (2/2)
T1
TW
T2
CLKOUT (Output)
<16>
<17>
A0 to A23 (Output) CSn (Output)
<22>
<23>
BCYST (Output)
<18>
<19>
RD, IORD (Output) [Read time] <20> <21>
UWR, LWR, IOWR (Output) [Write time] <26> <27>
D0 to D15 (I/O) [Read time]
<28>
<29>
D0 to D15 (I/O) [Write time] <25> <24> <24> <25>
WAIT (Input)
Remarks 1. This is the timing when the number of waits due to the DWC1 and DWC2 registers is zero. 2. The broken lines indicate high impedance. 3. n = 0, 3 to 5
Preliminary Data Sheet U15390EJ1V0DS
25
PD703130
(b) Read timing (SRAM, external ROM, or external I/O) (1/2)
Parameter Data input setup time (to address) Data input setup time (to RD) RD, IORD low-level width RD, IORD high-level width Delay time from address, CSn to RD, IORD Delay time from RD, IORD to address Data input hold time (from RD, IORD ) Delay time from RD, IORD to data output WAIT setup time (to address) WAIT setup time (to BCYST ) WAIT hold time (from BCYST ) Symbol <30> <31> <32> <33> <34> <35> <36> <37> <38> <39> <40> tSAID tSRDID tWRDL tWRDH tDARD tDRDA tHRDID tDRDOD tSAW tSBSW tHBSW Note Note Note 0 (1 + wD + w)T - 10 T - 10 0.5T - 10 (0.5 + i)T - 10 0 (0.5 + i)T - 10 T - 25 T - 25 Condition MIN. MAX. (1.5 + wD + w)T - 28 (1 + wD + w)T - 32 Unit ns ns ns ns ns ns ns ns ns ns ns
Note For first WAIT sampling when the number of waits due to the DWC1 and DWC2 registers is zero. Remarks 1. T = tCYK 2. w: The number of waits due to WAIT. 3. wD: The number of waits due to the DWC1 and DWC2 registers. 4. i: The number of idle states that are inserted when a write cycle follows a read cycle. 5. Maintain at least one of the data input hold times, tHKID or tHRDID. 6. n = 0, 3 to 5
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Preliminary Data Sheet U15390EJ1V0DS
PD703130
(b) Read timing (SRAM, external ROM, or external I/O) (2/2)
T1
TW
T2
CLKOUT (Output)
A0 to A23 (Output) CSn (Output)
UWR, LWR, IOWR (Output)
<33>
<32>
<35>
RD, IORD (Output) <34> <31> <30> <36> <37>
D0 to D15 (I/O)
<38>
WAIT (Input)
<39>
<40>
BCYST (Output)
Remarks 1. This is the timing when the number of waits due to the DWC1 and DWC2 registers is zero. 2. The broken lines indicate high impedance. 3. n = 0, 3 to 5
Preliminary Data Sheet U15390EJ1V0DS
27
PD703130
(c) Write timing (SRAM, external ROM, or external I/O) (1/2)
Parameter WAIT setup time (to address) WAIT setup time (to BCYST ) WAIT hold time (from BCYST ) Delay time from address, CSn to UWR, LWR, IOWR Address setup time (to UWR, LWR, IOWR ) Delay time from UWR, LWR, IOWR to address UWR, LWR, IOWR high-level width UWR, LWR, IOWR low-level width Data output setup time (to UWR, LWR, IOWR ) Data output hold time (from UWR, LWR, IOWR ) Symbol <38> <39> <40> <41> <42> <43> <44> <45> <46> <47> tSAW tSBSW tHBSW tDAWR tSAWR tDWRA tWWRH tWWRL tSODWR tHWROD Condition Note Note Note 0 0.5T - 10 (1.5 + wD + w)T - 10 0.5T - 10 T - 10 (1 + wD + w)T - 10 (1.5 + wD + w)T - 10 0.5T - 10 MIN. MAX. T - 25 T - 25 Unit ns ns ns ns ns ns ns ns ns ns
Note For first WAIT sampling when the number of waits due to the DWC1 and DWC2 registers is zero. Remarks 1. T = tCYK 2. w: The number of waits due to WAIT. 3. wD: The number of waits due to the DWC1 and DWC2 registers. 4. n = 0, 3 to 5
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Preliminary Data Sheet U15390EJ1V0DS
PD703130
(c) Write timing (SRAM, external ROM, or external I/O) (2/2)
T1
TW
T2
CLKOUT (Output)
A0 to A23 (Output) CSn (Output)
RD, IORD (Output) <42> <45> <43>
<41> <44>
UWR, LWR, IOWR (Output) <46> <47>
D0 to D15 (I/O)
<38>
WAIT (Input)
<39>
<40>
BCYST (Output)
Remarks 1. This is the timing when the number of waits due to the DWC1 and DWC2 registers is zero. 2. The broken lines indicate high impedance. 3. n = 0, 3 to 5
Preliminary Data Sheet U15390EJ1V0DS
29
PD703130
(d) DMA flyby transfer timing (SRAM external I/O transfer) (1/2)
Parameter WAIT setup time (to CLKOUT ) WAIT hold time (from CLKOUT ) RD low-level width RD high-level width Delay time from address, CSn to RD Delay time from RD to address Delay time from RD to data output WAIT setup time (to address) WAIT setup time (to BCYST ) WAIT hold time (from BCYST ) Delay time from address to IOWR Address setup time (to IOWR ) Delay time from IOWR to address IOWR high-level width IOWR low-level width Delay time from IOWR to RD Symbol <24> <25> <32> <33> <34> <35> <37> <38> <39> <40> <41> <42> <43> <44> <45> <48> tSWK tHKW tWRDL tWRDH tDARD tDRDA tDRDOD tSAW tSBSW tHBSW tDAWR tSAWR tDWRA tWWRH tWWRL tDWRRD wF = 0 wF = 1 Delay time from DMAAKm to IOWR Delay time from IOWR to DMAAKm <49> <50> tDDAWR tDWRDA Note Note Note 0 0.5T - 10 (1.5 + wD + w)T - 10 0.5T - 10 T - 10 (1 + wD + w)T - 10 0 T - 10 0.5T - 10 (0.5 + wF)T - 10 Condition MIN. 15 2 (1 + wD + wF + w)T - 10 T - 10 0.5T - 10 (0.5 + i)T - 10 (0.5 + i)T - 10 T - 25 T - 25 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note For first WAIT sampling when the number of waits due to the DWC1 and DWC2 registers is zero. Remarks 1. T = tCYK 2. w: The number of waits due to WAIT. 3. wD: The number of waits due to the DWC1 and DWC2 registers. 4. wF: The number of waits that are inserted for a source-side access during a DMA flyby transfer. 5. i: The number of idle states that are inserted when a write cycle follows a read cycle. 6. n = 0, 3 to 5, m = 0 to 3
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Preliminary Data Sheet U15390EJ1V0DS
PD703130
(d) DMA flyby transfer timing (SRAM external I/O transfer) (2/2)
T1 CLKOUT (Output)
TW
T2
A0 to A23 (Output) CSn (Output) <33> <32> <35>
RD (Output)
<34>
<48>
UWR, LWR (Output)
DMAAKm (Output)
<49>
<50>
IORD (Output) <42> <41> <44> IOWR (Output) <45> <43>
<37>
D0 to D15 (I/O) <38> <24> WAIT (Input) <40> <39> BCYST (Output) <25> <24> <25>
Remarks 1. This is the timing when the number of waits due to the DWC1 and DWC2 registers is zero and wF = 0. 2. The broken lines indicate high impedance. 3. n = 0, 3 to 5, m = 0 to 3
Preliminary Data Sheet U15390EJ1V0DS
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PD703130
(e) DMA flyby transfer timing (external I/O SRAM transfer) (1/2)
Parameter WAIT setup time (to CLKOUT ) WAIT hold time (from CLKOUT ) IORD low-level width IORD high-level width Delay time from address, CSn to IORD Delay time from IORD to address Delay time from IORD to data output WAIT setup time (to address) WAIT setup time (to BCYST ) WAIT hold time (from BCYST ) Delay time from address to UWR, LWR Address setup time (to UWR, LWR ) Delay time from UWR, LWR to address UWR, LWR high-level width UWR, LWR low-level width Delay time from UWR, LWR to IORD Symbol <24> <25> <32> <33> <34> <35> <37> <38> <39> <40> <41> <42> <43> <44> <45> <48> tSWK tHKW tWRDL tWRDH tDARD tDRDA tDRDOD tSAW tSBSW tHBSW tDAWR tSAWR tDWRA tWWRH tWWRL tDWRRD wF = 0 wF = 1 Delay time from DMAAKm to IORD Delay time from IORD to DMAAKm <51> <52> tDDARD tDRDDA Note Note Note 0 0.5T - 10 (1.5 + wD + w)T - 10 0.5T - 10 T - 10 (1 + wD + w)T - 10 0 T - 10 0.5T - 10 0.5T - 10 Condition MIN. 15 2 (1 + wD + wF + w)T - 10 T - 10 0.5T - 10 (0.5 + i)T - 10 (0.5 + i)T - 10 T - 25 T - 25 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note For first WAIT sampling when the number of waits due to the DWC1 and DWC2 registers is zero. Remarks 1. T = tCYK 2. w: The number of waits due to WAIT. 3. wD: The number of waits due to the DWC1 and DWC2 registers. 4. wF: The number of waits that are inserted for a source-side access during a DMA flyby transfer. 5. i: The number of idle states that are inserted when a write cycle follows a read cycle. 6. n = 0, 3 to 5, m = 0 to 3
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Preliminary Data Sheet U15390EJ1V0DS
PD703130
(e) DMA flyby transfer timing (external I/O SRAM transfer) (2/2)
T1 CLKOUT (Output)
TW
T2
A0 to A23 (Output) CSn (Output) <41> <44> UWR, LWR (Output) <42> <45> <43>
<48>
RD (Output)
<51>
<52>
DMAAKm (Output)
IOWR (Output) <34> <33> IORD (Output) <32> <35>
<37>
D0 to D15 (I/O) <38> <24> WAIT (Input) <40> <39> BCYST (Output) <25> <24> <25>
Remarks 1. This is the timing when the number of waits due to the DWC1 and DWC2 registers is zero and wF = 0. 2. The broken lines indicate high impedance. 3. n = 0, 3 to 5, m = 0 to 3
Preliminary Data Sheet U15390EJ1V0DS
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PD703130
(5) Page ROM access timing (1/2)
Parameter WAIT setup time (to CLKOUT ) WAIT hold time (from CLKOUT ) Data input setup time (to CLKOUT ) Data input hold time (from CLKOUT ) Off-page data input setup time (to address) Off-page data input setup time (to RD) Off-page RD low-level width RD high-level width Data input hold time (from RD) Delay time from RD to data output On-page RD low-level width On-page data input setup time (to address) On-page data input setup time (to RD) Symbol <24> <25> <26> <27> <30> <31> <32> <33> <36> <37> <53> <54> <55> tSWK tHKW tSKID tHKID tSAID tSRDID tWRDL tWRDH tHRDID tDRDOD tWORDL tSOAID tSORDID (1 + wD + w)T - 10 0.5T - 10 0 (0.5 + i)T - 10 (1.5 + wPR + w)T - 10 (1.5 + wPR + w)T - 28 (1.5 + wPR + w)T - 32 Condition MIN. 15 2 18 2 (1.5 + wD + w)T - 28 (1 + wD + w)T - 32 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
Remarks 1. T = tCYK 2. w: The number of waits due to WAIT. 3. wD: The number of waits due to the DWC1 and DWC2 registers. 4. wPR: The number of waits due to the PRC register. 5. i: The number of idle states that are inserted when a write cycle follows a read cycle. 6. Maintain at least one of the data input hold times, tHKID or tHRDID.
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Preliminary Data Sheet U15390EJ1V0DS
PD703130
(5) Page ROM access timing (2/2)
T1 CLKOUT (Output)
TDW
TW
T2
TO1
TPRW
TW
TO2
Off-page addressNote CSn (Output)
On-page addressNote <26> <30> UWR, LWR (Output) <33> <32> <31> RD (Output) <36> <26> <27> D0 to D15 (I/O) <25> <24> WAIT (Input) <24> <25> <24> <25> <24> <25> <27> <36> <53> <55> <37> <54>
BCYST (Output)
Note On-page and off-page addresses are as follows.
PRC Register MA5 0 0 0 1 MA4 0 0 1 1 MA3 0 1 1 1
On-page Addresses A0, A1 A0 to A2 A0 to A3 A0 to A4
Off-page Addresses A2 to A23 A3 to A23 A4 to A23 A5 to A23
Remarks 1. This is the timing for the following case. Number of waits due to the DWC1 and DWC2 registers (TDW): 1 Number of waits due to the PRC register (TPRW): 1 2. The broken lines indicate high impedance. 3. n = 0, 3 to 5
Preliminary Data Sheet U15390EJ1V0DS
35
PD703130
(6) DRAM access timing (a) Read timing (high-speed page DRAM access, normal access: off-page) (1/3)
Parameter WAIT setup time (to CLKOUT ) WAIT hold time (from CLKOUT ) Data input setup time (to CLKOUT ) Data input hold time (from CLKOUT ) Delay time from OE to data output Row address setup time Row address hold time Column address setup time Column address hold time Read/write cycle time RAS precharge time RAS pulse time RAS hold time Column address read time for RAS CAS pulse width CAS-RAS precharge time CAS hold time WE setup time WE hold time (from RAS ) WE hold time (from CAS ) CAS precharge time Output enable access time RAS access time Access time from column address CAS access time Symbol <24> <25> <26> <27> <37> <56> <57> <58> <59> <60> <61> <62> <63> <64> <65> <66> <67> <68> <69> <70> <71> <72> <73> <74> <75> tSWK tHKW tSKID tHKID tDRDOD tASR tRAH tASC tCAH tRC tRP tRAS tRSH tRAL tCAS tCRP tCSH tRCS tRRH tRCH tCPN tOEA tRAC tAA tCAC Condition MIN. 15 2 18 2 (0.5 + i)T - 10 (0.5 + wRP)T - 10 (0.5 + wRH)T - 10 0.5T - 10 (1.5 + wDA + w)T - 10 (3 + wRP + wRH + wDA + w)T - 10 (0.5 + wRP)T - 10 (2.5 + wRH + wDA + w)T - 10 (1.5 + wDA + w)T - 10 (2 + wDA + w)T - 10 (1 + wDA + w)T - 10 (1 + wRP)T - 10 (2 + wRH + wDA + w)T - 10 (2 + wRP + wRH)T - 10 0.5T - 10 T - 10 (2 + wRP + wRH)T - 10 (2 + wRP + wRH + wDA + w)T - 28 (2 + wRH + wDA + w)T - 28 (1.5 + wDA + w)T - 28 (1 + wDA + w)T - 28 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Remarks 1. T = tCYK 2. w: The number of waits due to WAIT. 3. wRP: The number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 4. wRH: The number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 5. wDA: The number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 6. i: The number of idle states that are inserted when a write cycle follows a read cycle.
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Preliminary Data Sheet U15390EJ1V0DS
PD703130
(a) Read timing (high-speed page DRAM access, normal access: off-page) (2/3)
Parameter RAS column address delay time RAS-CAS delay time Output buffer turn-off delay time (from OE ) Output buffer turn-off delay time (from CAS ) Symbol <76> <77> <78> <79> tRAD tRCD tOEZ tOFF Condition
MIN. MAX.
Unit ns ns ns ns
(0.5 + wRH)T - 10 (1 + wRH)T - 10 0 0
Remarks 1. T = tCYK 2. wRH: The number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13).
Preliminary Data Sheet U15390EJ1V0DS
37
PD703130
(a) Read timing (high-speed page DRAM access, normal access: off-page) (3/3)
TRPW CLKOUT (Output)
T1
TRHW
T2
TDAW
TW
T3
<58> <56> <57> <59>
A0 to A23 (Output)
Row address
Column address
<76> <61> <62>
<63> <64>
RASn (Output) <60> <77> <66> UCAS (Output) LCAS (Output) <71> <73> <68> <75> <70> <69> <67> <65>
WE (Output) <74> <72> <27> <37> <79>
OE (Output) <78> <26>
D0 to D15 (I/O) <24> <25> <24> <25>
WAIT (Input)
Remarks 1. This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13). Number of waits due to the RPCxx bit of the DRCn register (TRPW): 1 Number of waits due to the RHCxx bit of the DRCn register (TRHW): 1 Number of waits due to the DACxx bit of the DRCn register (TDAW): 1 2. The broken lines indicate high impedance. 3. n = 3 to 5
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Preliminary Data Sheet U15390EJ1V0DS
PD703130
[MEMO]
Preliminary Data Sheet U15390EJ1V0DS
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PD703130
(b) Read timing (high-speed page DRAM access: on-page) (1/2)
Parameter Data input setup time (to CLKOUT ) Data input hold time (from CLKOUT ) Delay time from OE to data output Column address setup time Column address hold time RAS hold time Column address read time for RAS CAS pulse width WE setup time (to CAS ) WE hold time (from RAS ) WE hold time (from CAS ) Output enable access time Access time from column address CAS access time Output buffer turn-off delay time (from OE ) Output buffer turn-off delay time (from CAS ) Access time from CAS precharge CAS precharge time High-speed page mode cycle time RAS hold time for CAS precharge Symbol <26> <27> <37> <58> <59> <63> <64> <65> <68> <69> <70> <72> <74> <75> <78> <79> <80> <81> <82> <83> tSKID tHKID tDRDOD tASC tCAH tRSH tRAL tCAS tRCS tRRH tRCH tOEA tAA tCAC tOEZ tOFF tACP tCP tPC tRHCP (1 + wCP)T - 10 (2 + wCP + wDA)T - 10 (2.5 + wCP + wDA)T - 10 0 0 (2 + wCP + wDA)T - 28 Condition MIN. 18 2 (0.5 + i)T - 10 (0.5 + wCP)T - 10 (1.5 + wDA)T - 10 (1.5 + wDA)T - 10 (2 + wCP + wDA)T - 10 (1 + wDA)T - 10 (1 + wCP)T - 10 0.5T - 10 T - 10 (1 + wCP + wDA)T - 28 (1.5 + wCP + wDA)T - 28 (1 + wDA)T - 28 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Remarks 1. T = tCYK 2. wCP: The number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 3. wDA: The number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 4. i: The number of idle states that are inserted when a write cycle follows a read cycle.
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Preliminary Data Sheet U15390EJ1V0DS
PD703130
(b) Read timing (high-speed page DRAM access: on-page) (2/2)
TCPW CLKOUT (Output)
TO1
TDAW
TO2
<58>
<59>
A0 to A23 (Output)
Column address
<63> <64>
RASn (Output) <83> <81> <65> <82> UCAS (Output) LCAS (Output) <69> <68> WE (Output) <75> <72> <26> <79> <37> <70>
OE (Output)
<74> <80> D0 to D15 (I/O)
<78> <27>
WAIT (Input)
Remarks 1. This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13). Number of waits due to the CPCxx bit of the DRCn register (TCPW): 1 Number of waits due to the DACxx bit of the DRCn register (TDAW): 1 2. The broken lines indicate high impedance. 3. n = 3 to 5
Preliminary Data Sheet U15390EJ1V0DS
41
PD703130
(c) Write timing (high-speed page DRAM access, normal access: off-page) (1/2)
Parameter WAIT setup time (to CLKOUT ) WAIT hold time (from CLKOUT ) Row address setup time Row address hold time Column address setup time Column address hold time Read/write cycle time RAS precharge time RAS pulse time RAS hold time Column address read time (from RAS ) CAS pulse width CAS-RAS precharge time CAS hold time CAS precharge time RAS column address delay time RAS-CAS delay time WE setup time (to CAS ) WE hold time (from CAS ) Data setup time (to CAS ) Data hold time (from CAS ) Symbol <24> <25> <56> <57> <58> <59> <60> <61> <62> <63> <64> <65> <66> <67> <71> <76> <77> <84> <85> <86> <87> tSWK tHKW tASR tRAH tASC tCAH tRC tRP tRAS tRSH tRAL tCAS tCRP tCSH tCPN tRAD tRCD tWCS tWCH tDS tDH Condition MIN. 15 2 (0.5 + wRP)T - 10 (0.5 + wRH)T - 10 0.5T - 10 (1.5 + wDA + w)T - 10 (3 + wRP + wRH + wDA + w)T - 10 (0.5 + wRP)T - 10 (2.5 + wRH + wDA + w)T - 10 (1.5 + wDA + w)T - 10 (2 + wDA + w)T - 10 (1 + wDA + w)T - 10 (1 + wRH)T - 10 (2 + wRH + wDA + w)T - 10 (2 + wRP + wRH)T - 10 (0.5 + wRH)T - 10 (1 + wRH)T - 10 (1 + wRP + wRH )T - 10 (1 + wDA + w)T - 10 (1.5 + wRP + wRH)T - 10 (1.5 + wDA + w)T - 10 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Remarks 1. T = tCYK 2. w: The number of waits due to WAIT. 3. wRP: The number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 4. wRH: The number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 5. wDA: The number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13).
42
Preliminary Data Sheet U15390EJ1V0DS
PD703130
(c) Write timing (high-speed page DRAM access, normal access: off-page) (2/2)
TRPW CLKOUT (Output)
T1
TRHW
T2
TDAW
TW
T3
<58> <56> <57> <59>
A0 to A23 (Output)
Row address
Column address
<76> <61> <62>
<63> <64>
RASn (Output) <60> <77> <66> UCAS (Output) LCAS (Output) <71> <67> <65>
OE (Output)
<84>
<85>
WE (Output)
<86>
<87>
D0 to D15 (I/O) <24> <25> <24> <25>
WAIT (Input)
Remarks 1. This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13). Number of waits due to the RPCxx bit of the DRCn register (TRPW): 1 Number of waits due to the RHCxx bit of the DRCn register (TRHW): 1 Number of waits due to the DACxx bit of the DRCn register (TDAW): 1 2. The broken lines indicate high impedance. 3. n = 3 to 5
Preliminary Data Sheet U15390EJ1V0DS
43
PD703130
(d) Write timing (high-speed page DRAM access: on-page) (1/2)
Parameter Column address setup time Column address hold time RAS hold time Column address read time (from RAS ) CAS pulse width CAS precharge time RAS hold time for CAS precharge WE setup time (to CAS ) WE hold time (from CAS ) Data setup time (to CAS ) Data hold time (from CAS ) WE read time (from RAS ) WE read time (from CAS ) Data setup time (to WE ) Data hold time (from WE ) WE pulse width Symbol <58> <59> <63> <64> <65> <81> <83> <84> <85> <86> <87> <88> <89> <90> <91> <92> tASC tCAH tRSH tRAL tCAS tCP tRHCP tWCS tWCH tDS tDH tRWL tCWL tDSWE tDHWE tWP wCP = 0 wCP = 0 wCP = 0 wCP = 0 wCP = 0 wCP 1 Condition MIN. (0.5 + wCP)T - 10 (1.5 + wDA)T - 10 (1.5 + wDA)T - 10 (2 + wCP + wDA)T - 10 (1 + wDA)T - 10 (1 + wCP)T - 10 (2.5 + wCP + wDA)T - 10 wCPT - 10 (1 + wDA)T - 10 (0.5 + wCP)T - 10 (1.5 + wDA)T - 10 (1.5 + wDA)T - 10 (1 + wDA)T - 10 0.5T - 10 (1.5 + wDA)T - 10 (1 + wDA)T - 10 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Remarks 1. T = tCYK 2. wCP: The number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 3. wDA: The number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13).
44
Preliminary Data Sheet U15390EJ1V0DS
PD703130
(d) Write timing (high-speed page DRAM access: on-page) (2/2)
TCPW CLKOUT (Output) TO1 TDAW TO2
<58>
<59>
A0 to A23 (Output)
Column address
<63> <64>
RASn (Output) <83> <81> UCAS (Output) LCAS (Output) <89> <88> <65>
OE (Output) <84> <92> <85>
WE (Output) <91> <90> <86> D0 to D15 (I/O) <87>
WAIT (Input)
Remarks 1. This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13). Number of waits due to the CPCxx bit of the DRCn register (TCPW ): 1 Number of waits due to the DACxx bit of the DRCn register (TDAW): 1 2. The broken lines indicate high impedance. 3. n = 3 to 5
Preliminary Data Sheet U15390EJ1V0DS
45
PD703130
(e) Read timing (EDO DRAM) (1/3)
Parameter Data input setup time (to CLKOUT ) Data input hold time (from CLKOUT ) Delay time from OE to data output Row address setup time Row address hold time Column address setup time Column address hold time RAS precharge time Column address read time (from RAS ) CAS-RAS precharge time CAS hold time WE setup time (to CAS ) WE hold time (from RAS ) WE hold time (from CAS ) RAS access time Access time from column address CAS access time Delay time from RAS to column address RAS-CAS delay time Output buffer turn-off delay time (from OE) Access time from CAS precharge CAS precharge time RAS hold time for CAS precharge Read cycle time RAS pulse width CAS pulse width CAS hold time from OE Off-page On-page Data input hold time (from CAS ) Symbol <26> <27> <37> <56> <57> <58> <59> <61> <64> <66> <67> <68> <69> <70> <73> <74> <75> <76> <77> <78> <80> <81> <83> <93> <94> <95> <96> <97> <98> tSKID tHKID tDRDOD tASR tRAH tASC tCAH tRP tRAL tCRP tCSH tRCS tRRH tRCH tRAC tAA tCAC tRAD tRCD tOEZ tACP tCP tRHCP tHPC tRASP tHCAS tOCH1 tOCH2 tDHC (0.5 + wCP)T - 10 (2 + wCP + wDA)T - 10 (1 + wDA + wCP)T - 10 (2.5 + wRH + wDA)T - 10 (0.5 + wDA)T - 10 (2 + wRH + wDA)T - 10 (0.5 + wDA)T - 10 0 (0.5 + wRH)T - 10 (1 + wRH)T - 10 0 (1.5 + wCP + wDA)T - 28 Condition MIN. 18 2 (0.5 + i)T - 10 (0.5 + wRP)T - 10 (0.5 + wRH)T - 10 0.5T - 10 (0.5 + wDA)T - 10 (0.5 + wRP)T - 10 (2 + wCP + wDA)T - 10 (1 + wRP)T - 10 (1.5 + wRH + wDA)T - 10 (2 + wRP + wRH)T - 10 0.5T - 10 1.5T - 10 (2 + wRH + wDA)T - 28 (1.5 + wDA)T - 28 (1 + wDA)T - 28 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Remarks 1. T = tCYK 2. wRP: The number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 3. wRH: The number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 4. wDA: The number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 5. wCP: The number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 6. i: The number of idle states that are inserted when a write cycle follows a read cycle.
46
Preliminary Data Sheet U15390EJ1V0DS
PD703130
(e) Read timing (EDO DRAM) (2/3)
Parameter Output enable access time Off-page On-page Symbol <99> <100> tOEA1 tOEA2 Condition MIN. MAX. (2 + wRP + wRH + wDA)T - 28 (1 + wCP + wDA)T - 28 Unit ns ns
Remarks 1. T = tCYK 2. wRP: The number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 3. wRH: The number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 4. wDA: The number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 5. wCP: The number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13).
Preliminary Data Sheet U15390EJ1V0DS
47
PD703130
(e) Read timing (EDO DRAM) (3/3)
TRPW CLKOUT (Output)
T1
TRHW
T2
TDAW TCPW
TB
TDAW
TE
<58> <56>
A0 to A23 (Output)
<57>
<59>
Column address Column address
Row address
<64> <76> <61>
RASn (Output)
<74> <94>
<67> <66>
UCAS (Output) LCAS (Output)
<83> <95> <81> <75>
<77>
<68>
<93> <80>
<95>
<69> <70>
WE (Output)
<97> <96>
Note OE (Output)
<100>
<26>
<37>
<75> <74>
D0 to D15 (I/O)
<98> <27>
Data
<27> <78>
Data
<26>
<73> <99>
BCYST (Output)
WAIT (Input)
Note For on-page access from another cycle during the RASn low-level signal. Remarks 1. This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13). Number of waits due to the RPCxx bit of the DRCn register (TRPW): 1 Number of waits due to the RHCxx bit of the DRCn register (TRHW): 1 Number of waits due to the DACxx bit of the DRCn register (TDAW): 1 Number of waits due to the CPCxx bit of the DRCn register (TCPW): 1 2. The broken lines indicate high impedance. 3. n = 3 to 5
48
Preliminary Data Sheet U15390EJ1V0DS
PD703130
[MEMO]
Preliminary Data Sheet U15390EJ1V0DS
49
PD703130
(f) Write timing (EDO DRAM) (1/2)
Parameter Row address setup time Row address hold time Column address setup time Column address hold time RAS precharge time RAS hold time Column address read time (from RAS ) CAS-RAS precharge time CAS hold time Delay time from RAS to column address RAS-CAS delay time CAS precharge time RAS hold time for CAS precharge WE hold time (from CAS ) Data hold time (from CAS ) WE read time (from RAS ) WE read time (from CAS ) WE pulse width Write cycle time RAS pulse width CAS pulse width WE setup time (to CAS ) Data setup time (to CAS ) Off-page On-page Off-page On-page On-page On-page On-page Symbol <56> <57> <58> <59> <61> <63> <64> <66> <67> <76> <77> <81> <83> <85> <87> <88> <89> <92> <93> <94> <95> <101> <102> <103> <104> tASR tRAH tASC tCAH tRP tRSH tRAL tCRP tCSH tRAD tRCD tCP tRHCP tWCH tDH tRWL tCWL tWP tHPC tRASP tHCAS tWCS1 tWCS2 tDS1 tDS2 wCP 1 wCP = 0 wCP = 0 wCP = 0 Condition MIN. (0.5 + wRP)T - 10 (0.5 + wRH)T - 10 0.5T - 10 (0.5 + wDA)T - 10 (0.5 + wRP)T - 10 (1.5 + wDA)T - 10 (2 + wCP + wDA)T - 10 (1 + wRP)T - 10 (1.5 + wRH + wDA)T - 10 (0.5 + wRH)T - 10 (1 + wRH)T - 10 (0.5 + wCP)T - 10 (2 + wCP + wDA)T - 10 (1 + wDA)T - 10 (0.5 + wDA)T - 10 (1.5 + wDA)T - 10 (0.5 + wDA)T - 10 (1 + wDA)T - 10 (1 + wDA + wCP)T - 10 (2.5 + wRH + wDA)T - 10 (0.5 + wDA)T - 10 (1 + wRP + wRH)T - 10 wCPT - 10 (1.5 + wRP + wRH)T - 10 (0.5 + wCP)T - 10 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Remarks 1. T = tCYK 2. wRP: The number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 3. wRH: The number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 4. wDA: The number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 5. wCP: The number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13).
50
Preliminary Data Sheet U15390EJ1V0DS
PD703130
(f) Write timing (EDO DRAM) (2/2)
TRPW
T1
TRHW
T2
TDAW
TCPW
TB
TDAW
TE
CLKOUT (Output) <58> <56> A0 to A23 (Output) <57> <59>
Column address
<58>
<59>
Column address
Row address
<76> <61> RASn (Output) <67> <66> UCAS (Output) LCAS (Output) <93> <89> <88> RD (Output) OE (Output) <102> <101> <92> WE (Output) <85> <77> <95> <81> <94>
<64>
<83> <63>
<95>
<85>
<103>
<87>
<104>
<87>
D0 to D15 (I/O)
Data
Data
BCYST (Output)
WAIT (Input)
Remarks 1. This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13). Number of waits due to the RPCxx bit of the DRCn register (TRPW): 1 Number of waits due to the RHCxx bit of the DRCn register (TRHW): 1 Number of waits due to the DACxx bit of the DRCn register (TDAW): 1 Number of waits due to the CPCxx bit of the DRCn register (TCPW): 1 2. The broken lines indicate high impedance. 3. n = 3 to 5
Preliminary Data Sheet U15390EJ1V0DS
51
PD703130
(g) DMA flyby transfer timing (DRAM (EDO, high-speed page) external I/O transfer) (1/3)
Parameter WAIT setup time (to CLKOUT ) WAIT hold time (from CLKOUT ) Delay time from OE to data output Delay time from address to IOWR Address setup time (to IOWR ) Delay time from IOWR to address Delay time from IOWR to RD Symbol <24> <25> <37> <41> <42> <43> <48> tSWK tHKW tDRDOD tDAWR tSAWR tDWRA tDWRRD wF = 0 wF = 1 IOWR low-level width Row address setup time Row address hold time Column address setup time Column address hold time Read/write cycle time RAS precharge time RAS hold time Column address read time for RAS CAS pulse width CAS-RAS precharge time CAS hold time <50> <56> <57> <58> <59> <60> <61> <63> <64> <65> <66> <67> tWWRL tASR tRAH tASC tCAH tRC tRP tRSH tRAL tCAS tCRP tCSH Condition MIN. 15 2 (0.5 + i)T - 10 (0.5 + wRP)T - 10 (2 + wRP + wRH + wDA + w)T - 10 0.5T - 10 0 T - 10 (2 + wRH + wDA + w)T - 10 (0.5 + wRP)T - 10 (0.5 + wRH)T - 10 0.5T - 10 (1.5 + wDA + wF + w)T - 10 (3 + wRP + wRH + wDA + wF + w)T - 10 (0.5 + wRP)T - 10 (1.5 + wDA + wF + w)T - 10 (2 + wCP + wDA + wF + w)T - 10 (1 + wDA + wF + w)T - 10 (1 + wRP)T - 10 (2 + wRH + wDA + wF + w)T - 10 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Remarks 1. T = tCYK 2. w: The number of waits due to WAIT. 3. wRP: The number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 4. wRH: The number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 5. wDA: The number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 6. wCP: The number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 7. wF: The number of waits that are inserted for a source-side access during a DMA flyby transfer. 8. i: The number of idle states that are inserted when a write cycle follows a read cycle.
52
Preliminary Data Sheet U15390EJ1V0DS
PD703130
(g) DMA flyby transfer timing (DRAM (EDO, high-speed page) external I/O transfer) (2/3)
Parameter WE setup time (to CAS ) WE hold time (from RAS ) WE hold time (from CAS ) CAS precharge time Delay time from RAS to column address RAS-CAS delay time Output buffer turn-off delay time (from OE ) Output buffer turn-off delay time (from CAS ) CAS precharge time High-speed page mode cycle time RAS hold time for CAS precharge RAS pulse width CAS hold time from OE (from CAS ) Off-page On-page Delay time from DMAAKm to CAS Delay time from IOWR to CAS Symbol <68> <69> <70> <71> <76> <77> <78> <79> <81> <82> <83> <94> <96> <97> <105> <106> tRCS tRRH tRCH tCPN tRAD tRCD tOEZ tOFF tCP tPC tRHCP tRASP tOCH1 tOCH2 tDDACS tDRDCS Condition MIN. (2 + wRP + wRH)T - 10 0.5T - 10 1.5T - 10 (2 + wRP + wRH)T - 10 (0.5 + wRH)T - 10 (1 + wRH)T - 10 0 0 (0.5 + wCP)T - 10 (2 + wCP + wDA + wF + w)T - 10 (2.5 + wCP + wDA + wF + w)T - 10 (2.5 + wRH + wDA + wF + w)T - 10 (2.5 + wRP + wRH + wDA + wF + w)T - 10 (1.5 + wCP + wDA + wF + w)T - 10 (1.5 + wRH)T - 10 (1 + wRH)T - 10 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Remarks 1. T = tCYK 2. w: The number of waits due to WAIT. 3. wCP: The number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 4. wDA: The number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 5. wRH: The number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 6. wRP: The number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 7. wF: The number of waits that are inserted for a source-side access during a DMA flyby transfer. 8. m = 0 to 3
Preliminary Data Sheet U15390EJ1V0DS
53
PD703130
(g) DMA flyby transfer timing (DRAM (EDO, high-speed page) external I/O transfer) (3/3)
TRPW
T1
TRHW
T2
TDAW
TW
T3
TCPW TO1 TDAW
TW
TO2
CLKOUT (Output)
<58> <56> <57> <59>
A0 to A23 (Output)
Row address
<76> <61>
Column address
<94> <60>
Column address
<64>
RASn (Output)
<77> <66> <67> <65> <81> <83> <63> <69>
UCAS (Output) LCAS (Output)
<71> <96> <82> <70> <79>
RD (Output) OE (Output)
<105> <48> <97>
DMAAKm (Output)
<68>
WE (Output)
IORD (Output)
<41>
<106> <42> <50>
<43>
<78> <37>
IOWR (Output)
<24>
D0 to D15 (I/O)
<25> <24>
Data
Data
<24> <25> <25>
WAIT (Input)
BCYST (Output)
Remarks 1. This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13). Number of waits due to the RPCxx bit of the DRCn register (TRPW): 1 Number of waits due to the RHCxx bit of the DRCn register (TRHW): 1 Number of waits due to the DACxx bit of the DRCn register (TDAW): 1 Number of waits due to the CPCxx bit of the DRCn register (TCPW): 1 Number of waits that are inserted for a source-side access during a DMA flyby transfer: 0 2. The broken lines indicate high impedance. 3. n = 3 to 5, m = 0 to 3
54
Preliminary Data Sheet U15390EJ1V0DS
PD703130
(h) DMA flyby transfer timing (external I/O DRAM (EDO, high-speed page) transfer) (1/3)
Parameter WAIT setup time (to CLKOUT ) WAIT hold time (from CLKOUT ) IORD low-level width IORD high-level width Delay time from address to IORD Delay time from IORD to address Row address setup time Row address hold time Column address setup time Column address hold time Read/write cycle time RAS precharge time RAS hold time Column address read time for RAS CAS pulse width CAS-RAS precharge time CAS hold time CAS precharge time Delay time from RAS to column address RAS-CAS delay time CAS precharge time High-speed page mode cycle time RAS hold time for CAS precharge WE hold time (from CAS ) WE read time (from RAS ) Symbol <24> <25> <32> <33> <34> <35> <56> <57> <58> <59> <60> <61> <63> <64> <65> <66> <67> <71> <76> <77> <81> <82> <83> <85> <88> tSWK tHKW tWRDL tWRDH tDARD tDRDA tASR tRAH tASC tCAH tRC tRP tRSH tRAL tCAS tCRP tCSH tCPN tRAD tRCD tCP tPC tRHCP tWCH tRWL wCP = 0 Condition MIN. 15 2 (2 + wRH + wDA + wF + w)T - 10 T - 10 0.5T - 10 (0.5 + i)T - 10 (0.5 + wRP)T - 10 (0.5 + wRH)T - 10 0.5T - 10 (1.5 + wDA + wF)T - 10 (3 + wRP + wRH + wDA + wF + w)T - 10 (0.5 + wRP)T - 10 (1.5 + wDA + wF)T - 10 (2 + wCP + wDA + wF + w)T - 10 (1 + wDA + wF)T - 10 (1 + wRP)T - 10 (2 + wRH + wDA + wF + w)T - 10 (2 + wRP + wRH + w)T - 10 (0.5 + wRH)T - 10 (1 + wRH + w)T - 10 (0.5 + wCP + w)T - 10 (2 + wCP + wDA + wF + w)T - 10 (2.5 + wCP + wDA + w)T - 10 (1 + wDA)T - 10 (1.5 + wDA + w)T - 10 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Remarks 1. T = tCYK 2. w: The number of waits due to WAIT. 3. wRH: The number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 4. wDA: The number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 5. wRP: The number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 6. wCP: The number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 7. wF: The number of waits that are inserted for a source-side access during a DMA flyby transfer. 8. i: The number of idle states that are inserted when a write cycle follows a read cycle.
Preliminary Data Sheet U15390EJ1V0DS
55
PD703130
(h) DMA flyby transfer timing (external I/O DRAM (EDO, high-speed page) transfer) (2/3)
Parameter WE read time (from CAS ) WE pulse width RAS pulse width WE setup time (to CAS ) Off-page On-page Symbol <89> <92> <94> <101> <102> <105> <106> <107> tCWL tWP tRASP tWCS1 tWCS2 tDDACS tDRDCS tDWERD wF = 0 wF = 1 wCP = 0 wCP 1 Condition wCP = 0 wCP = 0
MIN. MAX.
Unit ns ns ns ns ns ns ns ns ns
(1 + wDA + w)T - 10 (1 + wDA + w)T - 10 (2.5 + wRH + wDA + wF + w)T - 10 (1 + wRH + wRP + w)T - 10 wCPT - 10 (1.5 + wRH + w)T - 10 (1 + wRH + w)T - 10 0 T - 10
Delay time from DMAAKm to CAS Delay time from IORD to CAS Delay time from WE to IORD
Remarks 1. T = tCYK 2. w: The number of waits due to WAIT. 3. wRH: The number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 4. wDA: The number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 5. wRP: The number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 6. wCP: The number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to 13). 7. wF: The number of waits that are inserted for a source-side access during a DMA flyby transfer. 8. m = 0 to 3
56
Preliminary Data Sheet U15390EJ1V0DS
PD703130
(h) DMA flyby transfer timing (external I/O DRAM (EDO, high-speed page) transfer) (3/3)
TRPW CLKOUT (Output) <56> A0 to A23 (Output)
T1
TRHW
TW
T2
TDAW
T3
TCPW
TW
TO1
TDAW
TO2
<57>
<58>
<59> Column address <64> <94> <60>
Row address <76> <61>
Column address
RASn (Output) <77> <66> UCAS (Output) LCAS (Output) <71> <82> <83> RD (Output) OE (Output) <101> WE (Output) <105> DMAAKm (Output) <92> <85> <67> <65> <81> <63>
<102> <88> <89>
IOWR (Output) <106> <34> IORD (Output) <32> <25> D0 to D15 (I/O) <24> <24> WAIT (Input) <25> <33> Data <24> <25> Data <107> <35>
BCYST (Output)
Remarks 1. This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13). Number of waits due to the RPCxx bit of the DRCn register (TRPW): 1 Number of waits due to the RHCxx bit of the DRCn register (TRHW): 1 Number of waits due to the DACxx bit of the DRCn register (TDAW): 1 Number of waits due to the CPCxx bit of the DRCn register (TCPW): 1 Number of waits that are inserted for a source-side access during a DMA flyby transfer: 0 2. The broken lines indicate high impedance. 3. n = 3 to 5, m = 0 to 3
Preliminary Data Sheet U15390EJ1V0DS
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PD703130
(i) CBR refresh timing
Parameter RAS precharge time RAS pulse width CAS hold time RAS precharge CAS hold time CAS setup time Symbol <61> <62> <108> <110> <113> tRP tRAS tCHR tRPC tCSR Condition MIN. (1.5 + wRRW)T - 10 (1.5 + wRCW (1.5 + wRCW
Note Note
MAX.
Unit ns ns ns ns ns
)T - 10 )T - 10
(0.5 + wRRW)T - 10 T - 10
Note At least one clock cycle is inserted by default for wRCW regardless of the settings of the RCW0 to RCW2 bits of the RWC register. Remarks 1. T = tCYK 2. wRRW: The number of waits due to the RRW0 and RRW1 bits of the RWC register. 3. wRCW: The number of waits due to the RCW0 to RCW2 bits of the RWC register.
TRRW CLKOUT (Output)
T1
T2
TRCWNote
TRCW
T3
TI
<61>
<62>
RASn (Output) <110> <110> UCAS (Output) LCAS (Output) <113> <108>
Note This TRCW is always inserted regardless of the settings of the RCW0 to RCW2 bits of the RWC register. Remarks 1. This is the timing for the following case. Number of waits due to the RRW0 and RRW1 bits of the RWC register (TRRW): 1 Number of waits due to the RCW0 to RCW2 bits of the RWC register (TRCW): 2 2. n = 3 to 5
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Preliminary Data Sheet U15390EJ1V0DS
PD703130
(j) CBR self-refresh timing
Parameter CAS hold time RAS precharge time Symbol <114> <115> tCHS tRPS Condition MIN. -5 (1 + 2wSRW)T - 10 MAX. Unit ns ns
Remarks 1. T = tCYK 2. wSRW: The number of waits due to the SRW0 to SRW2 bits of the RWC register.
TRRW CLKOUT (Output)
TH
TH
TH
TRCW
TH
TI
TSRW
TSRW
<115>
RASn (Output)
<114>
UCAS (Output) LCAS (Output)
Output signals other than above
Remarks 1. This is the timing for the following case. Number of waits due to the RRW0 and RRW1 bits of the RWC register (TRRW): 1 Number of waits due to the RCW0 to RCW2 bits of the RWC register (TRCW): 1 Number of waits due to the SRW0 to SRW2 bits of the RWC register (TSRW): 2 2. The broken lines indicate high impedance. 3. n = 3 to 5
Preliminary Data Sheet U15390EJ1V0DS
59
PD703130
(7) DMAC timing
Parameter DMARQn setup time (to CLKOUT ) DMARQn hold time (from CLKOUT ) Symbol <116> <117> <118> DMAAKn output delay time (from CLKOUT ) DMAAKn output hold time (from CLKOUT ) TCn output delay time (from CLKOUT ) TCn output hold time (from CLKOUT ) <119> <120> <121> <122> tSDRK tHKDR1 tHKDR2 tDKDA tHKDA tDKTC tHKTC Condition
MIN. MAX.
Unit ns ns ns
15 2 Until DMAAKn 2 2 2 2 10 10 10 10
ns ns ns ns
Remark n = 0 to 3
CLKOUT (Output) <117> <116> DMARQn (Input) <116> <119> DMAAKn (Output) <120> <118>
<122> <121> TCn (Output)
Remark n = 0 to 3
60
Preliminary Data Sheet U15390EJ1V0DS
PD703130
[MEMO]
Preliminary Data Sheet U15390EJ1V0DS
61
PD703130
(8) Bus hold timing (1/2)
Parameter HLDRQ setup time (to CLKOUT ) HLDRQ hold time (from CLKOUT ) Delay time from CLKOUT to HLDAK HLDRQ high-level width HLDAK low-level width Delay time from CLKOUT to bus float Delay time from HLDAK to bus output Delay time from HLDRQ to HLDAK Delay time from HLDRQ to HLDAK Symbol <123> <124> <125> <126> <127> <128> <129> <130> <131> tSHRK tHKHR tDKHA tWHQH tWHAL tDKCF tDHAC tDHQHA1 tDHQHA2 0 2.5T 0.5T 1.5T Condition MIN. 15 2 2 T + 17 T-8 10 10 MAX. Unit ns ns ns ns ns ns ns ns ns
Remark T = tCYK
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Preliminary Data Sheet U15390EJ1V0DS
PD703130
(8) Bus hold timing (2/2)
T1 CLKOUT (Output)
<123>
T2
T3
TI
TH
TH
TH
TI
T1
<124> <123> <123> <123> <126>
<124>
HLDRQ (Input)
<125> <130> <125> <131>
HLDAK (Output)
<127> <128> <129>
A0 to A23 (Output)
Address
Undefined
D0 to D15 (I/O)
Data
CSn/RASm (Output)
BCYST (Output)
RD (Output)
WE (Output)
UCAS (Output) LCAS (Output)
WAIT (Input)
Remarks 1. The broken lines indicate high impedance. 2. n = 0, 3 to 5, m = 3 to 5
Preliminary Data Sheet U15390EJ1V0DS
63
PD703130
(9) Interrupt timing
Parameter NMI high-level width NMI low-level width INTPn high-level width INTPn low-level width Symbol <132> <133> <134> <135> tWNIH tWNIL tWITH tWITL Condition MIN. 500 500 4T + 10 4T + 10 MAX. Unit ns ns ns ns
Remarks 1. n = 100 to 103, 110 to 113, 130 2. T = tCYK
<132> <133>
NMI (Input)
<134>
<135>
INTPn (Input)
Remark n = 100 to 103, 110 to 113, 130 (10) RPU timing
Parameter TI13 high-level width TI13 low-level width TCLR1n high-level width TCLR1n low-level width Symbol <136> <137> <138> <139> tWTIH tWTIL tWTCH tWTCL Condition MIN. 3T + 18 3T + 18 3T + 18 3T + 18 MAX. Unit ns ns ns ns
Remarks 1. n = 0 to 2 2. T = tCYK
<136> <137>
TI13 (Input)
<138>
<139>
TCLR1n (Input)
Remark n = 0 to 2
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Preliminary Data Sheet U15390EJ1V0DS
PD703130
(11) UART0, UART1 timing (clock-synchronized or master mode only)
Parameter SCKn cycle SCKn high-level width SCKn low-level width RXDn setup time (to SCKn ) RXDn hold time (from SCKn ) TXDn output delay time (from SCKn ) TXDn output hold time (from SCKn ) Symbol <140> <141> <142> <143> <144> <145> <146> tCYSK0 tWSK0H tWSK0L tSRXSK tHSKRX tDSKTX tHSKTX 0.5tCYSK0 - 5 Condition Output Output Output MIN. 250 0.5tCYSK0 - 20 0.5tCYSK0 - 20 30 0 20 MAX. Unit ns ns ns ns ns ns ns
Remark n = 0, 1
<140> <142> <141>
SCKn (I/O)
<143>
<144>
RXDn (Input)
Input data
<145>
<146>
TXDn (Output)
Output data
Remarks 1. The broken lines indicate high impedance. 2. n = 0, 1
Preliminary Data Sheet U15390EJ1V0DS
65
PD703130
(12) CSI0, CSI1 timing (a) Master mode
Parameter SCKn cycle SCKn high-level width SCKn low-level width SIn setup time (to SCKn ) SIn hold time (from SCKn ) SOn output delay time (from SCKn ) SOn output hold time (from SCKn ) Symbol <147> <148> <149> <150> <151> <152> <153> tCYSK1 tWSK1H tWSK1L tSSISK tHSKSI tDSKSO tHSKSO 0.5tCYSK1 - 5 Condition Output Output Output MIN. 100 0.5tCYSK1 - 20 0.5tCYSK1 - 20 30 0 20 MAX. Unit ns ns ns ns ns ns ns
Remark n = 0, 1 (b) Slave mode
Parameter SCKn cycle SCKn high-level width SCKn low-level width SIn setup time (to SCKn ) SIn hold time (from SCKn ) SOn output delay time (from SCKn ) SOn output hold time (from SCKn ) Symbol <147> <148> <149> <150> <151> <152> <153> tCYSK1 tWSK1H tWSK1L tSSISK tHSKSI tDSKSO tHSKSO tWSK1H Condition Input Input Input MIN. 100 30 30 10 10 30 MAX. Unit ns ns ns ns ns ns ns
Remark n = 0, 1
<147> <149> <148>
SCKn (I/O)
<150>
<151>
Sln (Input)
Input data
<152>
<153>
SOn (Output)
Output data
Remarks 1. The broken lines indicate high impedance. 2. n = 0, 1
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Preliminary Data Sheet U15390EJ1V0DS
PD703130
A/D Converter Characteristics ( TA = -40 to +85C, VDD = CVDD = 3.0 to 3.6 V, HVDD = 5.0 V 10%, VSS = 0 V, HVDD - 0.5 V AVDD HVDD, output pin load capacitance: CL = 50 pF)
Parameter Resolution Overall error Quantization error Conversion time Sampling time Zero scale error Scale error Linearity error Analog input voltage Analog input resistance AVREF input voltage AVREF input current AVDD current Symbol - - - tCONV tSAMP - - - VIAN RAN AVREF AIREF AIDD AVREF = AVDD 4.5 -0.3 2 5.5 2.0 6 5 Conversion Note clock /6 4 4 3 AVREF + 0.3 Condition MIN. 10 4 1/2 10 TYP. MAX. Unit bit LSB LSB
s
ns LSB LSB LSB V M V mA mA
Note Conversion clock is the number of clocks set by the ADM1 register.
Preliminary Data Sheet U15390EJ1V0DS
67
PD703130
4. PACKAGE DRAWING
100-PIN PLASTIC LQFP (FINE PITCH) (14x14)
A B
75 76
51 50
detail of lead end S CD Q R
100 1
26 25
F G P H I
M
J K S
N
S L M
NOTE Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition.
ITEM A B C D F G H I J K L M N P Q R S
MILLIMETERS 16.000.20 14.000.20 14.000.20 16.000.20 1.00 1.00 0.22 +0.05 -0.04 0.08 0.50 (T.P.) 1.000.20 0.500.20 0.17 +0.03 -0.07 0.08 1.400.05 0.100.05 3 +7 -3 1.60 MAX.
S100GC-50-8EU, 8EA-2
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Preliminary Data Sheet U15390EJ1V0DS
PD703130
5. RECOMMENDED SOLDERING CONDITIONS
TBD
Preliminary Data Sheet U15390EJ1V0DS
69
PD703130
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Reference materials
Electrical Characteristics for Microcomputer (U15170J
Note
)
Note This document number is that of Japanese version. The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. V850E/MS1, V850E/MS2, and V850 Family are trademarks of NEC Corporation.
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Preliminary Data Sheet U15390EJ1V0DS
PD703130
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify:
* * * * *
Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements
*
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
NEC Electronics (Germany) GmbH
Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-3067-5800 Fax: 01-3067-5899 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490
NEC Electronics (France) S.A. NEC Electronics (UK) Ltd.
Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Madrid Office Madrid, Spain Tel: 091-504-2787 Fax: 091-504-2860
NEC Electronics Singapore Pte. Ltd.
Novena Square, Singapore Tel: 253-8311 Fax: 250-3583
NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l.
Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99
NEC Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388
Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division Guarulhos-SP, Brasil Tel: 11-6462-6810 Fax: 11-6462-6829
J01.2
Preliminary Data Sheet U15390EJ1V0DS
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PD703130
* The information contained in this document is being issued in advance of the production cycle for the device. The parameters for the device may change before final production or NEC Corporation, at its own discretion, may withdraw the device prior to its production. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. * NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. * Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. * While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. * NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.
M5 98. 8

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